Title :
Neuro chips with on-chip back-propagation and/or Hebbian learning
Author :
Shima, Takeshi ; Kimura, Tomohisa ; Kamatani, Yukio ; Itakura, Tetsuro ; Fujita, Yasuhiko ; Iida, Tetsuya
Author_Institution :
Toshiba Res. & Dev. Center, Kawasaki, Japan
fDate :
12/1/1992 12:00:00 AM
Abstract :
A layered neural net realized with two chips is described. One chip implements 24×24 synapses, a local weight control mechanism, and quantized ±1 LSB, both momentum and weight update schemes. The other contains 24 neurons, implementing not only backward propagation (BP) but Hebbian learning, with 200-pF drive capability. Some experimental chip characteristics verifying the implemented techniques are given
Keywords :
Hebbian learning; VLSI; analogue processing circuits; backpropagation; neural chips; VLSI; analogue chip; drive capability; layered neural net; local weight control mechanism; momentum update; neuro chip; on-chip back-propagation; synapses; weight update; Algorithm design and analysis; Analog circuits; Hebbian theory; Learning systems; Limiting; Neural networks; Neurons; Signal processing algorithms; Very large scale integration; Voltage;
Journal_Title :
Solid-State Circuits, IEEE Journal of
