A novel CMOS digital clock and data decoder

A novel CMOS digital clock and data decoder (DCDD) is described. The DCDD has been implemented in a commercial Ethernet serial interface (ESI) integrated circuit for the CSMA/CD standard. As a digital implementation, the DCDD is as manufacturable as conventional CMOS digital circuits, unlike decoders based on analog phase-locked loops, which are sensitive to CMOS processing parameters and are, hence, difficult to manufacture. A 32-tap synchronous delay line (SDL) provides the timing reference for the DCDD with a resolution equivalent to that provided by a 320-MHz clock. This phase information is used to digitally recover, using waveform synthesis performed at a 320-MHz rate, the clock and data information from the input data. The DCDD meets the jitter-tolerance requirements of the CSMA/CD standard with the consistency demanded of a commercial integrated circuit