DocumentCode
808407
Title
Activity-monitoring completion-detection (AMCD): a new approach to achieve self-timing
Author
Grass, E. ; Jones, S.
Author_Institution
Dept. of Electron. & Electr. Eng., Loughborough Univ. of Technol., UK
Volume
32
Issue
2
fYear
1996
fDate
1/18/1996 12:00:00 AM
Firstpage
86
Lastpage
88
Abstract
The feasibility of a new method called AMCD to achieve completion-detection for self-timed circuits has been demonstrated. The major advantage of the proposed method is that data dependent delays of CLs can be exploited whilst imposing only marginal repercussions on the CL itself. An analogue simulation of a 4×4 bit multiplier using models of a commercially available CMOS process has demonstrated the practicality of the approach. The results obtained clearly demonstrate the benefits of the method
Keywords
CMOS logic circuits; asynchronous circuits; combinational circuits; delays; multiplying circuits; 4 bit; 4×4 bit multiplier; CMOS process; activity-monitoring completion-detection; analogue simulation; asynchronous circuits; combinational logic blocks; data dependent delays; self-timed circuits;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el:19960068
Filename
490851
Link To Document