A DLL-biased, 14-bit DS analog-to-digital converter for GSM/GPRS/EDGE handsets

Author

Klemmer, Nikolaus ; Hegazi, Emad

Author_Institution

Ericsson Mobile Platforms, Research Triangle Park, NC, USA

Volume

41

Issue

2

fYear

2006

Firstpage

330

Lastpage

338

Abstract

A 14-bit analog-to-digital converter (ADC) design for GSM/GPRS/EDGE handsets is implemented in 0.25 μm CMOS. The measured SNR/SNDR/DR is 85.2/84.1/88 dB respectively. The modulator and the clock generator consume 1.05 mA from 2.7 V supply. A delay-locked-loop (DLL)-based bias scheme is implemented to guarantee that amplifier slewing takes a fixed percentage of the clock cycle over process corners, temperature, and clock frequency. The proposed biasing scheme is shown to minimize settling error variations and contain design margins.

Keywords

3G mobile communication; CMOS integrated circuits; analogue-digital conversion; cellular radio; delay lock loops; delta-sigma modulation; mobile handsets; modulators; packet radio networks; 0.25 micron; 1.05 mA; 14 bit; 2.7 V; CMOS process; EDGE handsets; GPRS handsets; GSM handsets; amplifier slewing; analog-to-digital converter; clock generator; delay locked loop; delta sigma modulation; modulator; settling error variations; Analog-digital conversion; Circuit noise; Clocks; GSM; Ground penetrating radar; Linearity; Noise figure; Noise level; Receivers; Telephone sets; Analog-to-digital converter (ADC); bias calibration; delta sigma; noise; switched capacitor;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2005.862355

Filename

1583797