Title :
A 32-mW 320-MHz continuous-time complex delta-sigma ADC for multi-mode wireless-LAN receivers
Author :
Arias, Jesus ; Kiss, Peter ; Prodanov, Vladimir ; Boccuzzi, Vito ; Banu, Mihai ; Bisbal, David ; Pablo, Jacinto San ; Quintanilla, Luis ; Barbolla, Juan
Author_Institution :
Dpto. de E. y Electron., Univ. de Valladolid, Spain
Abstract :
We present an experimental continuous-time complex delta-sigma multi-bit modulator, implemented in standard 0.25-μm CMOS technology and meeting all major requirements for application in IEEE 802.11a/b/g wireless LAN receivers. The clock frequency is 320 MHz, producing an oversampling ratio of 16 for 20 MHz channel bandwidths. The modulator supports two operation modes for zero-IF and low-IF receiver architectures respectively, requires a single 2.5-V power supply, and dissipates only 32 mW of power. The measured peak signal-to-noise ratio is 55 dB. Further experimental results using sine-wave and OFDM test signals are also presented.
Keywords :
CMOS integrated circuits; IEEE standards; OFDM modulation; analogue-digital conversion; delta-sigma modulation; integrated circuit design; modulators; radio receivers; wireless LAN; 0.25 micron; 2.5 V; 20 MHz; 32 mW; 320 MHz; 55 dB; CMOS technology; OFDM test signals; analogue-digital conversion; clock frequency; continuous-time complex modulator; delta-sigma modulator; low-IF receiver architectures; multibit modulator; multimode receivers; oversampling ratio; signal-to-noise ratio; sine-wave test signals; wireless-LAN receivers; zero-IF receiver architectures; Bandwidth; Baseband; CMOS technology; Circuits; Clocks; Dynamic range; Filters; OFDM modulation; Signal to noise ratio; Wireless LAN; Analog-to-digital conversion; sigma-delta modulation; wireless LAN;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2005.862346
