Title :
Novel circuits for radiation hardened memories
Author :
Haraszti, T.P. ; Mento, R.P. ; Moyer, N.E. ; Grant, W.M.
Author_Institution :
Microcirc Associates, Newport Beach, CA, USA
fDate :
10/1/1992 12:00:00 AM
Abstract :
Novel circuits, including orthogonal shuffle-type write-read arrays, error correction by weighted bidirectional codes, and associative iterative repair circuits, are proposed for significant improvements of the immunity of static RAMs, (SRAMs) against the effects of total dose and cosmic particle impacts for spaceborne mass storage systems. The implementation of the proposed circuit resulted in fault-tolerant 40-Mb and 10-Mb monolithic memories featuring a data rate of 120 MHz and power dissipation of 880 mW. These experimental serial-parallel memories were fabricated with a nonhardened standard CMOS processing technology, yet provided a total dose hardness of 1 Mrad and a projected single event upset rate of 1×1012 error/bit/day
Keywords :
CMOS integrated circuits; SRAM chips; aerospace instrumentation; radiation hardening (electronics); associative iterative repair circuits; cosmic particle impacts; error correction; monolithic memories; nonhardened standard CMOS processing technology; orthogonal shuffle-type write-read arrays; power dissipation; serial-parallel memories; spaceborne mass storage systems; static RAMs; weighted bidirectional codes; CMOS process; CMOS technology; Circuits; Error correction codes; Fault tolerance; Power dissipation; Radiation hardening; Random access memory; Single event upset; Space technology;
Journal_Title :
Nuclear Science, IEEE Transactions on
