DocumentCode :
808904
Title :
Scheduling for IC sort and test with preemptiveness via Lagrangian relaxation
Author :
Chen, Tsung-Rian ; Chang, Tsu-Shuan ; Chen, Cheng-Wu ; Kao, Jen
Author_Institution :
Dept. of Electr. & Comput. Eng., California Univ., Davis, CA, USA
Volume :
25
Issue :
8
fYear :
1995
fDate :
8/1/1995 12:00:00 AM
Firstpage :
1249
Lastpage :
1256
Abstract :
This paper presents a Lagrangian relaxation approach for the scheduling problem of an IC sort and test facility. In an integrated circuit (IC) manufacturing environment, a combination of tester, prober, and some hardware facilities is needed for wafer sort while a combination of tester, handler, and some other hardware facilities is needed for final test. To schedule both sorting and testing at the same time, the resource constraints on testers, probers, handlers and hardware have to be dealt with. This paper also extends the Lagrangian relaxation technique to solve a class of preemptive scheduling problems which particularly exist in an IC test floor environment. Numerical examples are given to illustrate the potential of the authors´ approach. Comparisons of the authors´ results with those obtained by some heuristic rules are also given
Keywords :
integrated circuit manufacture; integrated circuit testing; minimisation; production control; relaxation theory; resource allocation; IC sort and test facility; IC test floor environment; Lagrangian relaxation; hardware facilities; heuristic rules; integrated circuit manufacturing environment; preemptive scheduling; preemptiveness; prober; resource constraints; tester; wafer sort; Circuit testing; Hardware; Integrated circuit manufacture; Integrated circuit testing; Job shop scheduling; Lagrangian functions; Optimal scheduling; Performance evaluation; Sorting; Very large scale integration;
fLanguage :
English
Journal_Title :
Systems, Man and Cybernetics, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9472
Type :
jour
DOI :
10.1109/21.398686
Filename :
398686
Link To Document :
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