• DocumentCode
    809373
  • Title

    Simultaneous optimization of short-channel effects and junction capacitance in pMOSFET using large-angle-tilt-implantation of nitrogen (LATIN)

  • Author

    Kilho Lee ; Murthy, C. ; Rengarajan, R. ; Hegde, Saumya ; Jammy, R.

  • Author_Institution
    Infineon Technol., IBM Microelectron., Hopewell Junction, NY, USA
  • Volume
    23
  • Issue
    9
  • fYear
    2002
  • Firstpage
    547
  • Lastpage
    549
  • Abstract
    A widely used halo implant process of counter doping has a tradeoff between the short channel effects and the parasitic junction capacitance. We propose a novel drain engineering concept, large-angle-tilt-implantation of nitrogen (LATIN) to improve the short-channel effects without the increase of the junction capacitance in the buried-channel pMOSFET using sub-0.25-μm CMOS technology. We compare the electrical characteristics of devices fabricated using LATIN, a conventional arsenic halo implant process (As HALO), and BF2/sup +/ source/drain (S/D) implantation only. The LATIN improves the short-channel effects when compared to the case of BF2/sup +/ S/D implant only. In addition, the LATIN reduces junction capacitance by 18% when compared to As HALO. As a consequence, the LATIN is shown to be a drain engineering concept to simultaneously optimize the short-channel effects and junction capacitance. Calibrated two-dimensional simulations confirm the improvement with LATIN.
  • Keywords
    CMOS integrated circuits; MOSFET; boron; capacitance; integrated circuit technology; ion implantation; nitrogen; semiconductor process modelling; 0.25 micron; BF/sub 2//sup +/ source/drain implantation; CMOS technology; LATIN; N implantation; Si:BF/sub 2/; Si:N; TSUPREM4; buried-channel pMOSFET; calibrated 2D simulations; counter doping; drain engineering concept; electrical characteristics; halo implantation; large-angle-tilt implantation; parasitic junction capacitance; short-channel effects; simultaneous optimization; two-dimensional simulations; CMOS technology; Counting circuits; Implants; Jamming; MOSFET circuits; Microelectronics; Nitrogen; Parasitic capacitance; Process design; Silicon on insulator technology;
  • fLanguage
    English
  • Journal_Title
    Electron Device Letters, IEEE
  • Publisher
    ieee
  • ISSN
    0741-3106
  • Type

    jour

  • DOI
    10.1109/LED.2002.801324
  • Filename
    1028995