• DocumentCode
    809513
  • Title

    A fast partitioning method for PLA-based FPGAs

  • Author

    Hasan, Zafar ; Harrison, Dew ; Ciesielski, Maciej

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
  • Volume
    9
  • Issue
    4
  • fYear
    1992
  • Firstpage
    34
  • Lastpage
    39
  • Abstract
    A method for automatic multipartitioning of a multiple-output logic function into the smallest number of subfunctions for mapping to fixed-size PLAs of a field-programmable gate array (FPGA) chip is described. A detailed example to demonstrate the procedure is presented. It is shown that, for this example, the method produced almost optimum partitions in a fast and efficient manner.<>
  • Keywords
    circuit layout CAD; logic arrays; PLA-based FPGAs; almost optimum partitions; automatic multipartitioning; fast partitioning method; field-programmable gate array; fixed-size PLAs; multiple-output logic function; Field programmable gate arrays; Logic arrays; Logic functions; Programmable logic arrays;
  • fLanguage
    English
  • Journal_Title
    Design & Test of Computers, IEEE
  • Publisher
    ieee
  • ISSN
    0740-7475
  • Type

    jour

  • DOI
    10.1109/54.173331
  • Filename
    173331
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=809513