DocumentCode
809530
Title
Shortening the design cycle for programmable logic
Author
Kelem, Steven H. ; Seidel, Jorge P.
Author_Institution
Xilinx, San Jose, CA, USA
Volume
9
Issue
4
fYear
1992
Firstpage
40
Lastpage
50
Abstract
X-BLOX, a software tool for mapping architecture-independent designs to field-programmable gate arrays (FPGAs), is described. X-BLOX synthesizes a delay- and area-efficient logic-level design from an input specification consisting of a network of generic modules. The tool automatically propagates partial data type specification, performs architecture-specific design optimization, and performs context-dependent module synthesis.<>
Keywords
delays; logic CAD; logic arrays; software tools; X-BLOX; architecture-specific design optimization; context-dependent module synthesis; delays; design cycle; field-programmable gate arrays; generic modules; input specification; logic-level design; mapping architecture-independent designs; partial data type specification; programmable logic; software tool; Application specific integrated circuits; Circuit synthesis; Design methodology; Hardware design languages; Logic circuits; Logic design; Logic devices; Packaging machines; Programmable logic arrays; Programmable logic devices;
fLanguage
English
Journal_Title
Design & Test of Computers, IEEE
Publisher
ieee
ISSN
0740-7475
Type
jour
DOI
10.1109/54.173332
Filename
173332
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