DocumentCode
810493
Title
Linear algorithms for optimizing the layout of dynamic CMOS cells
Author
Lengauer, Thomas ; Müller, Rolf
Author_Institution
Univ. Gesamthochschule Paderborn, West Germany
Volume
35
Issue
3
fYear
1988
fDate
3/1/1988 12:00:00 AM
Firstpage
279
Lastpage
285
Abstract
In many CMOS design styles the basic building blocks are complex (static or dynamic) CMOS gates with up to a few dozen transistors. The layout optimization for such gates takes the shape of graph optimization problems. Two such graph problems, corresponding to different layout styles for basic cells composed of dynamic CMOS gates, are considered. Both problems are solved in linear time; the number of gates in the cell is considered
Keywords
CMOS integrated circuits; graph theory; integrated logic circuits; logic design; network topology; optimisation; dynamic CMOS cells; graph optimization problems; layout optimization; linear algorithms; logic design; logic gates; network topology; CMOS technology; Circuits; Conferences; Design optimization; Minimization; Optimizing compilers; Shape; Silicon compiler; Topology; Very large scale integration;
fLanguage
English
Journal_Title
Circuits and Systems, IEEE Transactions on
Publisher
ieee
ISSN
0098-4094
Type
jour
DOI
10.1109/31.1740
Filename
1740
Link To Document