Title :
Linear algorithms for optimizing the layout of dynamic CMOS cells
Author :
Lengauer, Thomas ; Müller, Rolf
Author_Institution :
Univ. Gesamthochschule Paderborn, West Germany
fDate :
3/1/1988 12:00:00 AM
Abstract :
In many CMOS design styles the basic building blocks are complex (static or dynamic) CMOS gates with up to a few dozen transistors. The layout optimization for such gates takes the shape of graph optimization problems. Two such graph problems, corresponding to different layout styles for basic cells composed of dynamic CMOS gates, are considered. Both problems are solved in linear time; the number of gates in the cell is considered
Keywords :
CMOS integrated circuits; graph theory; integrated logic circuits; logic design; network topology; optimisation; dynamic CMOS cells; graph optimization problems; layout optimization; linear algorithms; logic design; logic gates; network topology; CMOS technology; Circuits; Conferences; Design optimization; Minimization; Optimizing compilers; Shape; Silicon compiler; Topology; Very large scale integration;
Journal_Title :
Circuits and Systems, IEEE Transactions on
