Determination of intrinsic FET parameters using circuit partitioning approach

A technique useful in extracting intrinsic parameters for a compound semiconductor FET is presented. The technique makes use of a method provided by G. Dambrine et al. (1988). A modified active circuit that accounts for charge accumulation in the conducting channel is presented. The model has the further advantage of using control voltage modeling in agreement with the Curtice convention for large-signal analysis. The equations are presented for each active element as a function of the intrinsic y parameters. Measurements verify the parameter extraction technique with the circuit topology used and show good results