Title :
A BiCMOS dynamic multiplier using Wallace tree reduction architecture and 1.5-V full-swing BiCMOS dynamic logic circuit
Author :
Kuo, J.B. ; Su, K.W. ; Lou, J.H.
Author_Institution :
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
fDate :
8/1/1995 12:00:00 AM
Abstract :
The authors present a BiCMOS dynamic multiplier, which is free from race and charge-sharing problems, using Wallace tree reduction architecture and 1.5-V full-swing BiCMOS dynamic logic circuit. Based on a 1-μm BiCMOS technology, a 1.5-V 8×8 multiplier designed, shows a 2.3× improvement in speed as compared to the CMOS static one
Keywords :
BiCMOS digital integrated circuits; BiCMOS logic circuits; digital arithmetic; multiplying circuits; 1 micron; 1.5 V; BiCMOS dynamic logic circuit; BiCMOS dynamic multiplier; Wallace tree reduction architecture; Adders; BiCMOS integrated circuits; Bismuth; Buildings; CMOS technology; Digital systems; Logic circuits; Logic gates; Power supplies; Very large scale integration;
Journal_Title :
Solid-State Circuits, IEEE Journal of
