Title :
Processor implementations using queues
Author :
Milligan, Michael K. ; Cragon, Harvey G.
Author_Institution :
Dept. of Electr. Eng., Texas Univ., Austin, TX, USA
fDate :
8/1/1995 12:00:00 AM
Abstract :
For several decades, designers have used queues to resolve two processor-memory interface problems - long latency and low bandwidth. Here, we discuss the evolution of instruction and branch target queues. We also explore their use to support variable-length instructions and reduce misalignment problems. From the 1956 IBM 7030 (Stretch) to today´s PowerPC, we present queue configurations and prefetch strategies along with the design decisions that led to their final architectures
Keywords :
performance evaluation; queueing theory; branch target queues; long latency; low bandwidth; misalignment problems; prefetch strategies; processor implementations; processor-memory interface problems; queues; variable-length instructions; Bandwidth; Buffer storage; Cache memory; Clocks; Delay; Information retrieval; Prefetching;
Journal_Title :
Micro, IEEE
