A Multilevel Read and Verifying Scheme for Bi-NAND Flash Memories

Author

Chung, Chiu-Chiao ; Lin, Hongchin ; Lin, Yen-Tai

Author_Institution

Dept. of Electr. Eng., Nat. Chung-Hsing Univ., Taichung

Volume

42

Issue

5

fYear

2007

fDate

5/1/2007 12:00:00 AM

Firstpage

1180

Lastpage

1188

Abstract

A multilevel sensing and read verifying circuit is proposed for Bi-NAND (Buried bit-line NAND) type flash memories. The Bi-NAND technology employs the negative programmed threshold voltage to facilitate the multilevel storage with lower program/erase bias and programming disturbance. The sensing circuit utilizes an advanced cross-coupled sense amplifier to achieve excellent immunity against mismatch effect and reduction of power consumption. As well, it acts as data latch during multilevel sensing and verifying operations. By comparing to the conventional and simultaneous verifying circuits, the proposed scheme with dichotomous architecture simplifies the verifying circuit and speeds up verification process for multilevel operation. By adding only one latch and a pair of switches, the circuit can be easily expanded for one more bit per cell

Keywords

NAND circuits; flash memories; Bi-NAND flash memories; buried bit-line NAND; cross-coupled sense amplifier; data latch; dichotomous architecture; erase bias; lower program; mismatch effect; multilevel sensing; multilevel storage; negative programmed threshold voltage; power consumption reduction; programming disturbance; read verifying circuit; sensing circuit; switches; Energy consumption; Flash memory; Helium; Image storage; Latches; Power amplifiers; Switches; Switching circuits; Threshold voltage; Voltage control; Bi-NAND; Multilevel; dichotomous; flash memory; mismatch; negative programmed threshold voltage; read verifying;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2007.894822

Filename

4160064