DocumentCode :
811843
Title :
The Impact of Device Footprint Scaling on High-Performance CMOS Logic Technology
Author :
Deng, Jie ; Kim, Keunwoo ; Chuang, Ching-Te ; Wong, H. S Philip
Author_Institution :
Dept. of Electr. Eng., Stanford Univ., CA
Volume :
54
Issue :
5
fYear :
2007
fDate :
5/1/2007 12:00:00 AM
Firstpage :
1148
Lastpage :
1155
Abstract :
We propose selective scaling of device footprint for 65 nm and beyond CMOS technologies. The benefits of selective scaling of device footprint are illustrated using an ultrathin-body fully depleted silicon-on-insulator transistor as an example. We study the effect of footprint scaling on device, circuit, and system level performance. A complete 2D device structure is modeled for the numerical analysis. The results predict that an optimal footprint design can provide 30% smaller chip layout area, 20% faster speed, and 10% less dynamic power on overall chip performance benchmarked with a 53-bit pipelined multiplier. The variability analysis on both dc and ac characteristics indicates that the benefits of selective footprint scaling are not degraded by device variation
Keywords :
CMOS logic circuits; multiplying circuits; silicon-on-insulator; 2D device structure; 53 bit; 65 nm; CMOS logic technology; device footprint scaling; pipelined multiplier; ultrathin-body fully depleted silicon-on-insulator transistor; variability analysis; CMOS logic circuits; CMOS technology; Isolation technology; Leakage current; Logic devices; Numerical models; Parasitic capacitance; Power system modeling; Semiconductor device modeling; Silicon on insulator technology; CMOS; device footprint; device scaling; device variation; numerical simulation; selective scaling; ultrathin-body (UTB) fully depleted silicon-on-insulator (FD-SOI);
fLanguage :
English
Journal_Title :
Electron Devices, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9383
Type :
jour
DOI :
10.1109/TED.2007.894596
Filename :
4160100
Link To Document :
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