Analog PLL Design With Ring Oscillators at Low-Gigahertz Frequencies in Nanometer CMOS: Challenges and Solutions

This brief discusses the challenges and present techniques in designing analog phase-locked loops in nanometer CMOS. The primary challenges are the low supply voltage of 1 V or less, large gate leakage, and the high degree of process and temperature variability. The importance of tightening the free-running frequency of the oscillator in light of these challenges is highlighted first. Process and temperature compensation techniques for minimizing the variation of the free-running frequency of an oscillator are discussed. A rail-to-rail charge-pump with matched up/down currents and a capacitance multiplication technique for reducing the loop filter area are also discussed.