MOSFET´s with one-mask sealed diffusion-junctions for ULSI applications

Author

Liu, C.T. ; Chang, C.P. ; Lee, K.H. ; Liu, R.

Author_Institution

AT&T Bell Labs., Murray Hill, NJ, USA

Volume

16

Issue

8

fYear

1995

Firstpage

363

Lastpage

365

Abstract

We describe a One-mask Sealed Diffusion-junction (OSDiff) structure for ULSI applications. Shallow junctions are formed at temperatures /spl les/900/spl deg/C using a WSi/sub 2/ diffusion layer and sealed with a TiN barrier-layer before metallization. The TiN-WSi/sub 2/ stack is patterned in a single lithography step with oxide hard-masks and spacers. A phenomenon of boron diffusion retardation in the presence of phosphorus is observed in the SIMS data, and is utilized to reduce one mask step in implanting the junction areas. Transistor data also shows improved deep submicron performance when the LDD regions are formed at the same diffusion step which forms the S/D junctions without the additional LDD implantations. Only ten masks are required for a full-CMOS process with two-level metallization, and the circuit density and speed are also improved.<>

Keywords

CMOS integrated circuits; MOSFET; ULSI; integrated circuit metallisation; lithography; masks; 900 degC; LDD regions; MOSFET; SIMS data; TiN-WSi/sub 2/; ULSI applications; circuit density; deep submicron performance; full-CMOS process; one-mask sealed diffusion-junctions; oxide hard-masks; shallow junctions; single lithography step; two-level metallization; Boron; CMOS process; Contact resistance; Etching; Lithography; MOSFET circuits; Metallization; Temperature; Tin; Ultra large scale integration;

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/55.400739

Filename

400739