3D simulation of parasitic MOSFET effects for box isolation technologies

Author

Heiser, Gernot ; Poon, Simon ; Orlowski, Marius

Author_Institution

Motorola Inc., Austin, TX

Volume

38

Issue

12

fYear

1991

fDate

12/1/1991 12:00:00 AM

Firstpage

2721

Lastpage

2722

Abstract

Summary form only given. Despite the higher integration capability, trench isolation in MOS technologies presents a number of problems associated with the fabrication of deep trenches as well as problems arising from the electrical properties of the parasitic MOSFETs formed in conjunction with the trenches. The latter problem is addressed. The 3-D device simulator SECOND was used to quantify the contribution of both the lateral and vertical parasitic MOSFETs as a function of channel and well doping, trench width, and bias conditions. The I-V characteristics of all three MOSFETs as a function of technology parameters, are discussed along with derivation of design rules for box isolation technologies

Keywords

MOS integrated circuits; digital simulation; electronic engineering computing; insulated gate field effect transistors; semiconductor device models; 3D simulation; I-V characteristics; MOS technologies; SECOND; bias conditions; box isolation technologies; channel doping; design rules; parasitic MOSFET effects; technology parameters; trench isolation; trench width; well doping; Buffer layers; Current density; Etching; Gallium arsenide; Heterojunction bipolar transistors; III-V semiconductor materials; Isolation technology; Leakage current; MOSFET circuits; Zinc compounds;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.158760

Filename

158760