Switch-mode VAr compensator with minimized switching losses and energy storage elements

Author

He, Jin ; Mohan, Ned

Author_Institution

Dept. of Electr. Eng., Minnesota Univ., Minneapolis, MN, USA

Volume

5

Issue

1

fYear

1990

fDate

2/1/1990 12:00:00 AM

Firstpage

90

Lastpage

95

Abstract

A parallel-resonant DC link (PRDCL) circuit topology is proposed as an interface between DC voltage supply and the inverter to provide a short zero-voltage period in the DC link of the inverter to allow zero voltage switching in the switch-mode VAr compensator (SMVC). The circuit along with the SMVC can compensate for leading and lagging displacement power factors with a high switching frequency at significantly reduced switching losses. The new circuit is especially suitable for high-power SMVC applications using GTOs or other gate-turn-off devices. The circuit is analyzed in detail, and its operation principle is explained. Several design considerations are addressed, and the design formulas are obtained. The new topology and the overall system are verified by computer simulations

Keywords

energy storage; losses; static VAr compensators; switching; DC voltage supply; GTOs; SMVC; computer simulations; displacement power factors; energy storage elements; minimized switching losses; parallel-resonant DC link; short zero-voltage period; switch-mode VAr compensator; zero voltage switching; Application software; Circuit analysis; Circuit topology; Computer simulation; Inverters; Reactive power; Switching circuits; Switching frequency; Switching loss; Zero voltage switching;

fLanguage

English

Journal_Title

Power Systems, IEEE Transactions on

Publisher

ieee

ISSN

0885-8950

Type

jour

DOI

10.1109/59.49091

Filename

49091