SSMCB: Low-Power Variation-Tolerant Source-Synchronous Multicycle Bus

In this paper, a variation-tolerant low-power source-synchronous multicycle bus (SSMCB) interconnect scheme is proposed. This scheme is scalable and suitable for transferring data across different clock domains such as those in "many-core" SoCs and in 3-D ICs. SSMCB replaces intermediate flip-flops by a source-synchronous synchronization scheme. Removing the intermediate flip-flops in the SSMCB scheme enables better averaging of delay variations across the whole interconnect, which reduces bit-rate degradation due to within-die process variations. Monte Carlo circuit simulations show that SSMCB eliminates 90% of the variation-induced performance degradation in a six-cycle 9-mm-long 16-bit conventional bus. The proposed multicycle bus scheme also leads to significant energy savings due to the elimination of power-hungry flip-flops and the efficient design of the source synchronization overhead. Moreover, eliminating the intermediate flip-flops avoids the timing overhead of the setup time, the flip-flop delay, and the single-cycle clock jitter. This delay slack can then be translated into further energy savings by downsizing the repeaters. The significant delay jitter due to capacitive coupling has been addressed, and solutions are put forward to alleviate it. Circuit simulations in a 65-nm process environment indicate that energy savings up to 20% are achievable for a six-cycle 9-mm-long 16-bit bus.