DocumentCode :
812899
Title :
Examination of gradual-junction p-MOS structures for hot carrier control using a new lifetime extraction method
Author :
Doyle, Brian S. ; Mistry, Kaizad R. ; Jackson, Daniel B.
Author_Institution :
Digital Equipment Corp., Hudson, MA, USA
Volume :
39
Issue :
10
fYear :
1992
fDate :
10/1/1992 12:00:00 AM
Firstpage :
2290
Lastpage :
2297
Abstract :
The effect of junction engineering on the hot carrier lifetimes of p-MOS transistors is examined. A normalizing method for predicting lifetimes is developed and used to show that a critical parameter controlling the lifetimes of submicrometer p-MOS devices is the size of the hot-carrier-damaged region. This is verified on conventional and gradual-junction transistors, where different implant species and energies were used to alter the source and drain junction profiles. Conventional junction devices with gate currents up to 100 times larger than those of gradual junction devices were found to have the same lifetimes as gradual junctions devices for the same effective transistor length. It is concluded that, contrary to n-MOS transistors, controlling the size of the damage region is as important as, if not more important than, reducing the hot electron gate currents by junction engineering in p-MOS devices
Keywords :
MOS integrated circuits; carrier lifetime; hot carriers; insulated gate field effect transistors; semiconductor device models; damage region size control; gradual-junction transistors; hot carrier control; hot carrier lifetimes; hot electron gate currents; hot-carrier-damaged region; lifetime extraction method; lifetime prediction model; p-MOS structures; submicron PMOS devices; Aging; Circuits; Degradation; Electrons; Hot carriers; Implants; Prediction methods; Reliability engineering; Size control; Voltage;
fLanguage :
English
Journal_Title :
Electron Devices, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9383
Type :
jour
DOI :
10.1109/16.158801
Filename :
158801
Link To Document :
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