A stacked-CMOS cell technology for high-density SRAM´s

Author

Uemoto, Yasuhiro ; Fujii, Eiji ; Nakamura, Akira ; Senda, Kohji ; Takagi, Hiromitsu

Author_Institution

Matsushita Electron. Corp., Osaka, Japan

Volume

39

Issue

10

fYear

1992

fDate

10/1/1992 12:00:00 AM

Firstpage

2359

Lastpage

2363

Abstract

A stacked-CMOS SRAM cell technology for high-density SRAMs has been developed. It has been found that the increase of the on-current of the thin-film transistor (TFT) load leads not only to the increase of the cell noise margin, but also to the reduction of the cell area. The improvement of the electrical characteristics of the TFT load has been achieved by enlarging the grains of the polysilicon film through the use of a novel solid-phase growth technique. As a result, TFT loads with on/off current ratio of 10⁵ and off-current of 0.07 pA/μm, both promising for high-density SRAMs, have been obtained

Keywords

CMOS integrated circuits; SRAM chips; integrated circuit technology; solid phase epitaxial growth; thin film transistors; cell area reduction; cell noise margin; electrical characteristics; high-density SRAMs; off-current; on-current; on/off current ratio; polysilicon film grains; solid-phase growth; stacked-CMOS SRAM cell technology; Circuit noise; Degradation; Driver circuits; Electric variables; MOSFETs; Noise reduction; Random access memory; Solids; Thin film transistors; Voltage;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.158809

Filename

158809