• DocumentCode
    813273
  • Title

    Parallelised max-Log-Map model

  • Author

    Loo, K.K. ; Salman, K. ; Alukaidey, T. ; Jimaa, S.A.

  • Author_Institution
    Dept. of ECEE, Hertfordshire Univ., Hatfield, UK
  • Volume
    38
  • Issue
    17
  • fYear
    2002
  • fDate
    8/15/2002 12:00:00 AM
  • Firstpage
    971
  • Lastpage
    972
  • Abstract
    A parallelised max-Log-MAP model (P-max-Log-MAP) that exploits the sub-word parallelism and very long instruction word architecture of a microprocessor or a digital signal processor (DSP) is presented. The proposed model reduces considerably the computational complexity of the max-Log-MAP algorithm; and therefore facilitates easy implementation
  • Keywords
    computational complexity; decoding; parallel algorithms; signal processing; turbo codes; 3GPP turbo codes; DSP; VLIW architecture; computational complexity reduction; decoding; digital signal processor; max-Log-MAP algorithm; microprocessor; parallelised max-Log-MAP model; sub-word parallelism; very long instruction word architecture;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:20020663
  • Filename
    1031791
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=813273