Limits to binary logic switch scaling - a gedanken model

Author

Zhirnov, Victor V. ; Cavin, Ralph K., III ; Hutchby, James A. ; Bourianoff, George I.

Author_Institution

Semicond. Res. Corp., Res. Triangle Park, NC, USA

Volume

91

Issue

11

fYear

2003

fDate

11/1/2003 12:00:00 AM

Firstpage

1934

Lastpage

1939

Abstract

In this paper we consider device scaling and speed limitations on irreversible von Neumann computing that are derived from the requirement of "least energy computation." We consider computational systems whose material realizations utilize electrons and energy barriers to represent and manipulate their binary representations of state.

Keywords

CMOS logic circuits; MOSFET; integrated circuit modelling; integrated circuit packaging; nanoelectronics; switching theory; CMOS technology; MOS transistors; binary logic switch scaling limits; binary representations of state; closely packed devices; computational systems; device scaling; digital integrated circuits; energy barriers; gedanken model; heat removal; irreversible von Neumann computing; least energy computation; material realizations; nanotechnology; power consumption; speed limitations; CMOS technology; Digital integrated circuits; Digital systems; Energy barrier; Integrated circuit technology; Logic devices; Nanotechnology; Power dissipation; Switches; Throughput;

fLanguage

English

Journal_Title

Proceedings of the IEEE

Publisher

ieee

ISSN

0018-9219

Type

jour

DOI

10.1109/JPROC.2003.818324

Filename

1240081