Title :
A 60-GHz Dual-Mode Class AB Power Amplifier in 40-nm CMOS
Author :
Dixian Zhao ; Reynaert, Patrick
Author_Institution :
Dept. of Electr. Eng., Univ. of Leuven, Leuven, Belgium
Abstract :
A 60-GHz dual-mode power amplifier (PA) is implemented in 40-nm bulk CMOS technology. To boost the amplifier performance at millimeter-wave (mmWave) frequencies, a new transistor layout is proposed to minimize the device and interconnect parasitics while the neutralized amplifier stage is co-optimized with input transformer to improve the power gain and stability. The transformer-based power-combining PA consists of two unit amplifiers, operating in Class AB for better back-off efficiency. To further reduce the power consumption and hence extend battery lifetime, one unit PA is tuned off in low-power mode. A switch is used to short the output of this non-operating unit PA to reduce the combiner loss and improve the efficiency. The PA achieves a measured saturated output power (PSAT) of 17.0 dBm (12.1 dBm) and 1-dB compressed power (P1dB) of 13.8 dBm (9.1 dBm) in the high-power (low-power) mode. The power-added efficiencies (PAEs) at PSAT and P1dB are 30.3% and 21.6% respectively for the high-power mode. Compared to Class A, the PA operating in Class AB shows 5.3% improvement in measured PAE at P1dB with no compromise in linearity. The PA with the power combiner only occupies an active area of 0.074 mm 2. The reliability measurements are also conducted and the PA has an estimated lifetime of 80613 hours.
Keywords :
CMOS analogue integrated circuits; circuit stability; field effect MIMIC; low-power electronics; microwave switches; millimetre wave power amplifiers; millimetre wave power transistors; power combiners; transformers; battery lifetime; bulk CMOS technology; dual-mode class AB power amplifier; efficiency 21.6 percent; efficiency 30.3 percent; frequency 60 GHz; high-power mode; input transformer; interconnect parasitics; low-power mode; neutralized amplifier stage; nonoperating unit PA; power consumption; power gain; power-added efficiency; reliability measurements; size 40 nm; switch; transformer-based power-combining PA; transistor layout; unit amplifiers; CMOS integrated circuits; Layout; Logic gates; Metals; Stability analysis; Thermal stability; Transistors; 60 GHz; AM-PM distortion; CMOS; Class AB; Power amplifier; device parasitics; hot carrier injection; impedance matching; linearity; load pull; millimeter- wave; power combining; power-added efficiency (PAE); reliability; transformer; two-tone test;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2013.2275662