• DocumentCode
    813891
  • Title

    Analysis and optimization of structured power/ground networks

  • Author

    Su, Haihua ; Gala, Kaushik H. ; Sapatnekar, Sachin S.

  • Author_Institution
    IBM, Austin, TX, USA
  • Volume
    22
  • Issue
    11
  • fYear
    2003
  • Firstpage
    1533
  • Lastpage
    1544
  • Abstract
    This paper presents an efficient method for optimizing power/ground (P/G) networks by widening wires and adding decoupling capacitors (decaps). It proposes a structured skeleton that is intermediate to the conventional method that uses full meshes, which are hard to analyze efficiently, and tree-structured networks, which provide poor performance. As an example, we consider a P/G network structure modeled as an overlying mesh with underlying trees originating from the mesh, which eases the task of analysis with acceptable performance sacrifices. A fast and efficient event-driven P/G network simulator is proposed, which hierarchically simulates the P/G network with an adaptation of PRIMA to handle nonzero initial conditions. An adjoint network that incorporates the variable topology of the original P/G network, as elements switch in and out of the network, is constructed to calculate the transient adjoint sensitivity over multiple intervals. The gradients of the most critical node with respect to each wire width and decap are used by a sensitivity-based heuristic optimizer that minimizes a weighted sum of the wire and the decap area. Experimental results show that this procedure can be used to efficiently optimize large networks.
  • Keywords
    CMOS integrated circuits; circuit CAD; circuit optimisation; integrated circuit design; mesh generation; network topology; wiring; CMOS; PRIMA; adjoint network; circuit optimization; circuit topology; decap area; decoupling capacitors; most critical node; multiple intervals; nonzero initial conditions; overlying mesh; reduced order systems; sensitivity-based heuristic optimizer; structured power/ground networks; transient adjoint sensitivity; variable topology; weighted sum; wire width; wires; Capacitors; Circuits; Current density; Discrete event simulation; Network topology; Optimization methods; Performance analysis; Power grids; Switches; Wire;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/TCAD.2003.818372
  • Filename
    1240091