Title :
Time division multiplexing with orthogonal RAMs
Author :
Cooperman, M. ; Sieber, R. ; Moolenbeek, R.
Author_Institution :
GTE Labs. Inc., Waltham, MA, USA
fDate :
4/1/1988 12:00:00 AM
Abstract :
A technique for time-division multiplexing is described. Multiplexing and demultiplexing is achieved with a type of memory array in which reading is performed orthogonally to writing. The orthogonal memory provides storage and serial-to-parallel (plus parallel-to-serial) conversion in a regular and compact structure. This results in reduced chip area, reduced power dissipation, and an increased speed-density product, making the scheme ideal for VLSI implementation. The orthogonal RAM has been implemented in 1.2-μm CMOS, and basic operation has been validated
Keywords :
CMOS integrated circuits; VLSI; digital communication systems; integrated memory circuits; multiplexing equipment; random-access storage; time division multiplexing; 1.2 micron; CMOS; TDM; VLSI implementation; chip area reduction; compact structure; demultiplexing; digital transmission; memory array; orthogonal RAM; parallel/serial conversion; serial/parallel conversion; time-division multiplexing; Biomedical signal processing; Finite impulse response filter; Narrowband; Notice of Violation; Signal processing algorithms; Speech processing; Spread spectrum communication; Time division multiplexing; Transversal filters; Wiener filter;
Journal_Title :
Circuits and Systems, IEEE Transactions on
