Title :
Circuit-level simulation of TDDB failure in digital CMOS circuits
Author :
Minami, Eric R. ; Kuusinen, Scott B. ; Rosenbaum, Elyse ; Ko, Ping K. ; Hu, Chenming
fDate :
8/1/1995 12:00:00 AM
Abstract :
An efficient circuit-level simulator for the prediction of time-dependent dielectric breakdown effects in digital CMOS circuits has been developed and integrated into the reliability simulation tool BERT (Berkeley Reliability Tools). The new module enhances the capability of the earlier SPICE-based oxide breakdown simulator by enabling practical simulations of large digital circuits. We discuss burn-in simulation for digital circuits and show that a significant reduction in oxide breakdown failure probability is possible
Keywords :
CMOS digital integrated circuits; circuit analysis computing; electric breakdown; failure analysis; integrated circuit reliability; BERT; Berkeley Reliability Tools; TDDB failure; burn-in simulation; circuit-level simulator; digital CMOS circuits; large digital circuit simulation; oxide breakdown failure probability; oxide stress voltage; reliability simulation tool; time-dependent dielectric breakdown effects; Bit error rate; CMOS digital integrated circuits; CMOS logic circuits; Circuit simulation; Digital circuits; Electric breakdown; Integrated circuit reliability; Predictive models; SPICE; Stress;
Journal_Title :
Semiconductor Manufacturing, IEEE Transactions on
