Architecture, design, and application of an event-based test system

In this paper, we present the architecture, design, and usage of a new type of semiconductor IC test system. The traditional IC test systems require conversion of design simulation data (vectors) into cyclized form, such as WGL or STIL format. The new architecture described in this paper avoids such conversion and uses design simulation data as-is. Thus, it allows testing in the design simulation environment (Verilog/VHDL). The basic architecture, design, implementation, and testing of this tester is described at individual component levels as well as at the system level. Finally, its unique test flow and usage models are presented.