A pipelined A/D conversion technique with near-inherent monotonicity

A simple pipelined A/D conversion technique, which provides superior monotonicity to that of conventional pipelined converters is presented. The technique involves simple re-arrangement of the feedback capacitor. Unlike existing techniques, it does not add circuit complexity, increase power consumption, or sacrifice conversion speed. On the contrary, the technique allows the use of smaller capacitors for a given differential linearity target, thereby reducing the power consumption while maintaining the speed. The technique is applicable to pipelined architectures with a wide range of bits per stage including 1-b/stage. Monte Carlo simulation indicates that at 3-σ levels, 0.781% capacitor mismatch combined with 1.56%-of-full-scale comparator errors provides over 95.2% 12-b yield in a 2-b/stage architecture