Interconnect capacitance characterization using charge-injection-induced error-free (CIEF) charge-based capacitance measurement (CBCM)

Author

Chang, Yao-Wen ; Chang, Hsin-Wen ; Lu, Tao-Cheng ; King, Ya-Chin ; Ting, WenChi ; Ku, Yen-Hui Joseph ; Lu, Chih-Yuan

Author_Institution

Macronix Int. Co., Ltd, Hsinchu, Taiwan

Volume

19

Issue

1

fYear

2006

Firstpage

50

Lastpage

56

Abstract

In this work, we describe a novel operation of charge-injection-induced error-free charge-based capacitance measurement (CIEF CBCM) method. This method has the simplest test structure among various CBCM methods by using only one N/PMOS pair. CIEF CBCM has the advantage of being free from charge-injection-induced errors and of efficient layout area usage. It is very suitable for industrial applications for large amounts of accurate capacitance characterizations with a limited layout area. Besides, CIEF CBCM is also implemented for investigating the impact of floating dummy metal fills on interconnect capacitance directly from silicon data.

Keywords

capacitance measurement; charge injection; charge-coupled devices; integrated circuit interconnections; NIPMOS pair; accurate capacitance characterization; charge injection; charge-based capacitance measurement; charge-injection-induced error-free; efficient layout area usage; floating dummy metal fill; interconnect capacitance characterization; limited layout area; silicon data; Capacitance measurement; Charge measurement; Circuit synthesis; Current measurement; Integrated circuit interconnections; Parasitic capacitance; Probes; Semiconductor device measurement; Silicon; Testing; Capacitance measurement; charge injection; charge-based capacitance measurement (CBCM); interconnect capacitance;

fLanguage

English

Journal_Title

Semiconductor Manufacturing, IEEE Transactions on

Publisher

ieee

ISSN

0894-6507

Type

jour

DOI

10.1109/TSM.2005.863228

Filename

1588862