A Delta-Sigma Modulator With a Widely Programmable Center Frequency and 82-dB Peak SNDR

In this paper, analysis and design of a four-bit fourth- order delta-sigma modulator with a widely programmable center frequency are presented. Novel methods for quantizing and implementing the digitally programmable modulator coefficients enable performance comparable to state-of-the-art discrete-time fixed- frequency modulators at any center frequency from DC to 0.31 fs in steps of 0.0052 fs. The 0.18 mum 1.8 V CMOS prototype implemented in a silicon area of 4.5 mm ² consumes 115 mW at a sampling frequency of 40 MHz. The SNDR and SNR over a 310 kHz bandwidth range from 71 dB to 82 dB and from 76 dB to 86 dB, respectively.