The reliability of systems with two levels of fault tolerance: the return of the `birthday surprise´

Author

Yang, Guu-chang ; Fuja, Tom

Author_Institution

Dept. of Electr. Eng., Nat. Chung Hsing Univ., Taichung, Taiwan

Volume

41

Issue

11

fYear

1992

fDate

11/1/1992 12:00:00 AM

Firstpage

1490

Lastpage

1496

Abstract

The reliability of systems that employ fault tolerance at two different hierarchical levels is considered. It is assumed that the system consists of a two-dimensional array of components. Each component is reliable as long as it has been afflicted by no more than t faults; when t+1 faults occur in a particular component, the component ceases to be reliable. Furthermore, the system remains operative as long as no more than one component in any row is unreliable. Generalizing the techniques used to analyze the well-known `birthday surprise´ problem of applied probability makes it possible to derive an approximation to the average number of faults needed until the system fails. Applications include random access memory systems with chip-level and board-level coding as well as fault-tolerant systolic arrays

Keywords

encoding; fault tolerant computing; random-access storage; systolic arrays; board-level coding; chip level coding; fault tolerance; fault-tolerant systolic arrays; hierarchical levels; random access memory systems; reliability; two-dimensional array; Control systems; Error correction; Error correction codes; Failure analysis; Fault tolerance; Fault tolerant systems; Random access memory; Read-write memory; Redundancy; Systolic arrays;

fLanguage

English

Journal_Title

Computers, IEEE Transactions on

Publisher

ieee

ISSN

0018-9340

Type

jour

DOI

10.1109/12.177320

Filename

177320