A Memory Efficient Partially Parallel Decoder Architecture for Quasi-Cyclic LDPC Codes

Author

Wang, Zhongfeng ; Cui, Zhiqiang

Author_Institution

Sch. of Electr. Eng. & Comput. Sci., Oregon State Univ., Corvallis, OR

Volume

15

Issue

4

fYear

2007

fDate

4/1/2007 12:00:00 AM

Firstpage

483

Lastpage

488

Abstract

This paper presents a memory efficient partially parallel decoder architecture suited for high rate quasi-cyclic low-density parity-check (QC-LDPC) codes using (modified) min-sum algorithm for decoding. In general, over 30% of memory can be saved over conventional partially parallel decoder architectures. Efficient techniques have been developed to reduce the computation delay of the node processing units and to minimize hardware overhead for parallel processing. The proposed decoder architecture can linearly increase the decoding throughput with a small percentage of extra hardware. Consequently, it facilitates the applications of LDPC codes in area/power sensitive high-speed communication systems

Keywords

cyclic codes; error correction codes; parallel architectures; parity check codes; area/power sensitive high-speed communication systems; error correction codes; memory efficient partially parallel decoder architecture; min-sum algorithm; parallel processing; quasicyclic LDPC codes; quasicyclic low-density parity-check codes; Computer architecture; Concurrent computing; Delay; Error correction codes; Hardware; Iterative decoding; Parallel processing; Parity check codes; Quantum cascade lasers; Throughput; Architecture; error correction codes; low-density parity check (LDPC); memory efficient; quasi-cyclic (QC) codes;

fLanguage

English

Journal_Title

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on

Publisher

ieee

ISSN

1063-8210

Type

jour

DOI

10.1109/TED.2007.895247

Filename

4162517