Title :
An improved technique for circuit board interconnect test
Author_Institution :
IBM Corp., Austin, TX, USA
fDate :
10/1/1992 12:00:00 AM
Abstract :
The author reviews the self-test features of the IBM RISC System/6000 processor circuit board. Based on this, a technique is described to automate the interconnect wiring test, which is performed as part of the power-on self-test (POST) at the manufacturing stage. Essential to the implementation is the idea of response compression using the multiple input signature registers (MISR). Interconnect wiring defects are diagnosed by comparing the content of the MISR with the expected result after a simple test procedure. Formal analysis shows that a high test coverage can be achieved for the most commonly occurring defects. As a result, the proposed technique has the advantages of low overhead cost and easy fault detection
Keywords :
IBM computers; built-in self test; computer equipment testing; computer testing; electric connectors; fault location; logic testing; printed circuit accessories; printed circuit testing; reduced instruction set computing; shift registers; system buses; BIST; IBM RISC System/6000 processor circuit board; circuit board interconnect; fault detection; formal analysis; interconnect wiring test; multiple input signature registers; overhead cost; power-on self-test; response compression; signature analysis; walking test sequence; wiring defects; Automatic testing; Built-in self-test; Circuit testing; Integrated circuit interconnections; Manufacturing automation; Performance evaluation; Power system interconnection; Printed circuits; Reduced instruction set computing; Wiring;
Journal_Title :
Instrumentation and Measurement, IEEE Transactions on
