A Manufacturing Cost Model for 3-D Monolithic Memory Integrated Circuits

Imminent lateral scaling issues with NAND Flash are forcing manufacturers to consider 3-D process integration to keep single chip memory capacities rising while keeping costs down. In this way, several layers of memory cells are stacked on top of a silicon substrate using a single series of process steps with no material bonding used. This paper presents a general and practical cost model showing the advantages of 3-D process integration together with the main parameters determining the total cost. This model suggests that a mini revolution will soon be upon us consisting of multiprogrammable stacked nonvolatile memory cells in a monolithic chip.