DocumentCode
815802
Title
Improving test effectiveness of scan-based BIST by scan chain partitioning
Author
Xiang, Dong ; Chen, Ming-Jing ; Sun, Jia-Guang ; Fujiwara, Hideo
Author_Institution
Sch. of Software, Tsinghua Univ., Beijing, China
Volume
24
Issue
6
fYear
2005
fDate
6/1/2005 12:00:00 AM
Firstpage
916
Lastpage
927
Abstract
Test effectiveness of a test-per-scan built-in self-test (BIST) scheme is highly dependent on the length and number of scan chains. Fewer cycles are used to capture test responses when the length of the scan chains increases and the total number of clock cycles is fixed. Another important feature of the test-per-scan BIST scheme is that test responses of the circuit at the inputs of the scan flip-flops are not observable during the shift cycles. A new scan architecture is proposed to make a scan-based circuit more observable. The scan chain is partitioned into multiple segments. Multiple capture cycles are inserted to receive test responses during the shift cycles compared to the test-per-scan test scheme. Unlike other BIST schemes using multiple capture cycles after the shift cycles, our method inserts multiple capture cycles inside the shift cycles, but not after the shift cycles. Unlike the previous method that drives multiple scan segments by a single scan-in signal, the proposed method uses a new architecture to control all scan segments by different signals. Sufficient experimental results are presented to demonstrate the effectiveness of the method.
Keywords
built-in self test; flip-flops; logic partitioning; logic testing; built-in self-test; multiple capture cycles; scan chain partitioning; scan flip-flops; scan-based BIST; scan-based circuit; test effectiveness; test responses; test-per-scan test; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Clocks; Flip-flops; Microelectronics; Sun; System testing; Timing; Scan-based built-in self-test (BIST); scan chain partitioning; test-per-clock; test-per-scan;
fLanguage
English
Journal_Title
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher
ieee
ISSN
0278-0070
Type
jour
DOI
10.1109/TCAD.2005.847943
Filename
1432882
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