Ultra low power 2.4-GHz 0.35-μm CMOS dual-modulus prescaler design

Author

Chong-Chon Ng ; Kwok-Keung M Cheng

Author_Institution

Dept. of Electron. Eng., Chinese Univ. of Hong Kong, China

Volume

16

Issue

2

fYear

2006

Firstpage

75

Lastpage

77

Abstract

This letter presents the design and implementation of a dual-modulus (64/65) prescaler based upon the phase-switching technique. Low power consumption is achieved by using one dynamic flip-flop in the full-speed divide-by-four circuit and no power-hungry synchronizing circuits to tackle the glitch problem. The proposed design is fabricated using 0.35-μm standard CMOS process and is measured to operate from 2.08-2.66GHz with power dissipation of less than 1mW.

Keywords

CMOS digital integrated circuits; UHF integrated circuits; integrated circuit design; logic design; low-power electronics; prescalers; 0.35 micron; 2.06 to 2.66 GHz; CMOS; divide-by-four circuit; dual-modulus prescaler; dynamic flip-flop; frequency divider; phase switching; phase-locked loop; power consumption; Circuits; Clocks; Complexity theory; Energy consumption; Frequency conversion; Frequency synchronization; Latches; Phase locked loops; Power dissipation; Radio frequency; Dual-modulus prescaler (DMP); frequency divider; phase switching; phase-locked loop (PLL);

fLanguage

English

Journal_Title

Microwave and Wireless Components Letters, IEEE

Publisher

ieee

ISSN

1531-1309

Type

jour

DOI

10.1109/LMWC.2005.863223

Filename

1588942