DocumentCode :
81599
Title :
Divide-by-Three Injection-Locked Frequency Dividers Over 200 GHz in 40-nm CMOS
Author :
Pin-Hao Feng ; Shen-Iuan Liu
Author_Institution :
Grad. Inst. of Electron. Eng. & Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Volume :
48
Issue :
2
fYear :
2013
fDate :
Feb. 2013
Firstpage :
405
Lastpage :
416
Abstract :
Four divide-by-3 injection-locked frequency dividers (ILFDs) are fabricated in 40-nm CMOS technology. A second-harmonic peaking technique is used to enhance the locking range. The distributed inductor technique is used to enhance the operation frequency and the locking range. The locking range and design considerations of the proposed ILFDs are discussed. The largest measured locking range among four ILFDs is 236.6~245.2 GHz. The highest operation frequency is over 280 GHz. These ILFDs consume 2.97~3.96 mW from a supply of 1.1 V excluding output buffers.
Keywords :
CMOS analogue integrated circuits; frequency dividers; inductors; millimetre wave integrated circuits; CMOS technology; ILFD; design considerations; distributed inductor technique; divide-by-three injection-locked frequency dividers; frequency 236.6 GHz to 245.2 GHz; locking range; operation frequency; power 2.97 mW to 3.96 mW; second-harmonic peaking technique; size 40 nm; voltage 1.1 V; Harmonic analysis; Inductance; Inductors; Layout; Mixers; Transistors; Distributed inductor; divide-by-three; injection-locked frequency divider (ILFD); millimeter-wave;
fLanguage :
English
Journal_Title :
Solid-State Circuits, IEEE Journal of
Publisher :
ieee
ISSN :
0018-9200
Type :
jour
DOI :
10.1109/JSSC.2012.2223932
Filename :
6365767
Link To Document :
بازگشت