A yield improvement technique for IC layout using local design rules

Author

Allan, Gerard A. ; Walton, Anthony J. ; Holwill, Robert J.

Author_Institution

Dept. of Electr. Eng., Edinburgh Univ., UK

Volume

11

Issue

11

fYear

1992

fDate

11/1/1992 12:00:00 AM

Firstpage

1355

Lastpage

1362

Abstract

The concept of local design rules is introduced. These are integrated circuit (IC) layout rules that define the optimum feature size and spacing in relation to the surrounding geometry and are used to increase the yield of ICs. The impact of these rules on the performance and reliability of ICs is discussed. Algorithms that enable the automatic application of track displacement, track width, and contact size local design rules to IC layout are presented. Simulation results are provided for some layout examples

Keywords

circuit layout CAD; circuit reliability; integrated circuit technology; CAD; IC layout; contact size; integrated circuit; local design rules; optimum feature size; reliability; spacing; track displacement; track width; yield improvement; Application specific integrated circuits; Circuit simulation; Computational geometry; Conductors; Contacts; Design optimization; Helium; Integrated circuit layout; Integrated circuit reliability; Integrated circuit yield;

fLanguage

English

Journal_Title

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Publisher

ieee

ISSN

0278-0070

Type

jour

DOI

10.1109/43.177399

Filename

177399