DocumentCode
816125
Title
Optimized synthesis of asynchronous control circuits from graph-theoretic specifications
Author
Vanbekbergen, Peter ; Goossens, Gert ; Catthoor, Francky ; De Man, Hugo J.
Author_Institution
IMEC Lab., Leuven, Belgium
Volume
11
Issue
11
fYear
1992
fDate
11/1/1992 12:00:00 AM
Firstpage
1426
Lastpage
1438
Abstract
The proposed synthesis method starts from a graph-theoretic specification called a signal transition graph (STG). A method for transforming a given STG into an STG that satisfies the original timing behavior and that in addition obeys the unique state coding requirement is given. It is shown that in general, many valid solutions to this problem are possible. Therefore, an attempt is made to find a transformed STG that can be realized in a circuit with optimized speed and area
Keywords
asynchronous sequential logic; graph theory; logic CAD; asynchronous control circuits; graph-theoretic specifications; signal transition graph; state coding requirement; synthesis method; timing behavior; Asynchronous circuits; Circuit faults; Circuit synthesis; Clocks; Concurrent computing; Design automation; Hazards; Laboratories; Signal synthesis; Timing;
fLanguage
English
Journal_Title
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher
ieee
ISSN
0278-0070
Type
jour
DOI
10.1109/43.177405
Filename
177405
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