DocumentCode
816129
Title
Associative processors for video coding applications
Author
Balam, Subhash ; Schonfeld, Dan
Author_Institution
Qualcomm Inc., San Diego, CA, USA
Volume
16
Issue
2
fYear
2006
Firstpage
241
Lastpage
250
Abstract
Associative processors are single-instruction multiple-data-based architectures that provide huge parallelism which can be very useful for processing video in real time. This paper describes architectural requirements for video and shows that associative processors are ideally suited for applications involving video. Some routines like discrete cosine transforms (DCTs) lack required parallelism and their implementation becomes critical for the overall performance of the processor for video. We present three different approaches for computing two-dimensional DCT on associative processors and discuss their implementation details. Many methods like conditional execution of DCT, have been suggested in literature for power efficiency. In this paper, we discuss integration of these techniques in our implementation. Finally, performance of Associative processors is compared with that of RISC and DSP processor and show that associative processors are better suited for processing video both in terms of speed and power.
Keywords
data compression; discrete cosine transforms; video coding; associative processors; discrete cosine transforms; single-instruction multiple-data-based architectures; video coding applications; Discrete cosine transforms; Frequency; Motion estimation; Parallel processing; Quantization; Reduced instruction set computing; Streaming media; Video coding; Video compression; Video sequences; Associative processors; content-addressable memory (CAM); discrete cosine transform (DCT); video;
fLanguage
English
Journal_Title
Circuits and Systems for Video Technology, IEEE Transactions on
Publisher
ieee
ISSN
1051-8215
Type
jour
DOI
10.1109/TCSVT.2005.858696
Filename
1588964
Link To Document