Title :
Optimized test application timing for AC test
Author :
Iyengar, Vijay S. ; Vijayan, Gopalakrishnan
Author_Institution :
IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
fDate :
11/1/1992 12:00:00 AM
Abstract :
The problems associated with optimization of the test application timing for a class of test equipment are identified. Two approaches to test application timing are introduced. The notion of slack is used to define the objective function for optimization. The optimization problem is shown to be NP-complete even for nonreconvergent-fanout circuits. Heuristics for the optimization problems are presented, and the results are compared with bounds on test circuits
Keywords :
combinatorial circuits; computational complexity; electronic equipment testing; graph theory; integrated circuit testing; logic testing; optimisation; sequential circuits; test equipment; AC test; NP-complete; delay fault testing; multiple assignment problem; nonreconvergent-fanout circuits; objective function; optimization problem; single assignment problem; test application timing; test equipment; Assembly; Circuit faults; Circuit simulation; Circuit testing; Delay; Integrated circuit technology; Integrated circuit testing; Logic testing; Test equipment; Timing;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
