Title :
A 400-MT/s 6.4-GB/s multiprocessor bus interface
Author :
Muljono, Harry ; Lee, Beom-Taek ; Tian, Yanmei Kathy ; Wang, Yanbin Eddie ; Atha, Mubeen ; Huang, Tiffany ; Adachi, Mitsuhiro ; Rusu, Stefan
Author_Institution :
Intel Corp., Santa Clara, CA, USA
Abstract :
This paper describes the design of a system bus interface for the 130-nm Itanium®2 processor that operates at 400MT/s (1 megatransfer = 1 Mb/s/pin) with a peak bandwidth of 6.4 GB/s. The high-speed operation is achieved by employing source-synchronous transfer with differential strobes. Short flight time is accomplished by double-sided placement of the processors. Preboost and postboost edge-rate control enables fast clock-to-output timing with tight edge-rate range. The built-in input/output (I/O) loopback test feature enables I/O parameters to be tested on die, using a delay-locked loop and interpolator with 21-ps phase-skew error and 15-ps rms jitter. Power modeling methodology facilitates accurate prediction of system performance.
Keywords :
delay lock loops; high-speed integrated circuits; interpolation; microprocessor chips; parallel architectures; system buses; timing jitter; 130 nm; 21 ps; 6.4 GB/s; I/O parameters; Itanium 2 processor; clock-to-output timing; delay-locked loop; differential strobes; double-sided placement; flight time; high-speed operation; interpolator; jitter; multiprocessor bus interface; phase-skew error; postboost edge-rate control; preboost edge-rate control; source-synchronous transfer; system bus interface; system performance; tight edge-rate range; Bandwidth; Clocks; Delay; Jitter; Power system modeling; Predictive models; System buses; System performance; Testing; Timing;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2003.818295
