DocumentCode
816206
Title
Efficient high-speed/low-power line-based architecture for two-dimensional discrete wavelet transform using lifting scheme
Author
Xiong, Cheng-yi ; Tian, Jin-Wen ; Liu, Jian
Volume
16
Issue
2
fYear
2006
Firstpage
309
Lastpage
316
Abstract
Efficient line-based architectures for two-dimensional discrete wavelet transform (2-D DWT) are presented in this paper. We first present a four-input/four-output architecture for direct 2-D DWT that 1-level decomposition of a N×N image could be performed in approximately N2/4 intra-working clock cycles (ccs), where the parallelism among four subbands transforms in lifting-based 2-D DWT is explored. By using this four-input/four-output architecture, we propose a novel pipelined architecture for multilevel 2-D DWT that can perform a complete dyadic decomposition of N×N image in approximately N2/4 ccs. Performance analysis and comparison results demonstrate that, the proposed architectures have faster throughput rate and good performance in terms of production of throughput rate and hardware cost, as well as hardware utilization. The proposed pipelined architecture could be an efficient alternative for high-speed and/or low-power applications.
Keywords
discrete wavelet transforms; image processing; pipeline processing; power cables; four-input four-output architecture; high-speed low-power line-based architecture; lifting scheme; pipelined architecture; two-dimensional discrete wavelet transform; Carbon capture and storage; Computer architecture; Discrete Fourier transforms; Discrete wavelet transforms; Fast Fourier transforms; Hardware; Image coding; Image processing; Signal analysis; Throughput; Discrete wavelet transform (DWT); high-speed/lower power; lifting scheme; pipelined;
fLanguage
English
Journal_Title
Circuits and Systems for Video Technology, IEEE Transactions on
Publisher
ieee
ISSN
1051-8215
Type
jour
DOI
10.1109/TCSVT.2005.860121
Filename
1588972
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