Stacked 3-D Fin-CMOS technology

Author

Wu, Xusheng ; Chan, Philip C.H. ; Zhang, Shengdong ; Feng, Chuguang ; Chan, Mansun

Author_Institution

Dept. of Electr. & Electron. Eng., Hong Kong Univ. of Sci. & Technol., China

Volume

26

Issue

6

fYear

2005

fDate

6/1/2005 12:00:00 AM

Firstpage

416

Lastpage

418

Abstract

A stacked three-dimensional Fin-CMOS (SF-CMOS) technology has been proposed and implemented. The technology is based on a double-layer SOI wafer formed by performing two oxygen implants to form two single-crystal silicon films with isolation layer in between. The proposed approach achieves a 50% area reduction and significant shortening of wiring distance between the active devices when compared with existing planar CMOS technology. The SF-CMOS technology also inherits the scalability and two-dimensional processing compatibility of the FinFET architecture.

Keywords

CMOS integrated circuits; integrated circuit technology; silicon-on-insulator; 3D integrated circuits; SF-CMOS technology; Si; double SIMOX; double-layer SOI wafer; finFET; isolation layer; oxygen implants; silicon-on-insulator; single-crystal silicon films; stacked 3D fin-CMOS technology; CMOS technology; Doping; FinFETs; Implants; Integrated circuit technology; Isolation technology; Semiconductor films; Silicon; Three-dimensional integrated circuits; Wiring; CMOS; FinFET; double SIMOX; silicon-on-insulator (SOI); three-dimensional (3-D) integrated circuits;

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/LED.2005.848070

Filename

1432917