Title :
A 1.2-V 1.5-Gb/s 72-Mb DDR3 SRAM
Author :
Cho, Uk-Rae ; Kim, Tae-Hyoung ; Yoon, Yong-Jin ; Lee, Jong-Cheol ; Bae, Dae-Gi ; Kim, Nam-Seog ; Kim, Kang-Young ; Son, Young-Jae ; Yang, Jeong-Suk ; Sohn, Kwon-Il ; Kim, Sung-Tae ; Lee, In-Yeol ; Lee, Kwang-Jin ; Kang, Tae-Gyoung ; Kim, Su-Chul ; Ahn, Ke
Author_Institution :
SRAM Memory Div., Samsung Electron., Gyeonggi-Do, South Korea
Abstract :
A 1.2-V 72-Mb double data rate 3 (DDR3) SRAM achieves a data rate of 1.5 Gb/s using dynamic self-resetting circuits. Single-ended main data lines halve the data line precharging power dissipation and the number of data lines. Clocks phase shifted by 0°, 90°, and 270° are generated through the proposed clock adjustment circuits. The latter circuits make input data sampled with an optimized setup/hold window. On-chip input termination with a linearity error of ±4.1% is developed to improve signal integrity at higher data rates. A 1.2-V 1.5-Gb/s 72-Mb DDR3 SRAM is fabricated in a 0.10-μm CMOS process with five metals. The cell size and the chip size are 0.845 μm2 and 151.1 mm2, respectively.
Keywords :
CMOS memory circuits; SRAM chips; circuit optimisation; high-speed integrated circuits; integrated circuit design; memory architecture; synchronisation; 0.10 micron; 1.2 V; 1.5 Gbit/s; 72 Mbit; CMOS process; DDR3 SRAM; cell size; chip size; clock adjustment circuits; data line precharging power dissipation; double data rate 3 SRAM; dynamic self-resetting circuits; high-speed SRAM; input data sampling; linearity error; on-chip input termination; optimized setup/hold window; phase shifted clocks; signal integrity; single-ended main data lines; CMOS memory circuits; CMOS process; CMOS technology; Clocks; Impedance; Linearity; Network servers; Power dissipation; Random access memory; Workstations;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2003.818137
