Fast ADC

A novel ADC is described, consisting in its simplest and fastest version of a parallel ADC supplying the most significant bits, plus several suitably-connected difference amplifiers in which the input signal undergoes successive folding. Their common output is fed into another parallel ADC which supplies the least significant bits. The conversion rate is of the order of 400 MHz for eight bits. Several versions are described, yielding different trade-offs between speed and the number of discriminators employed.