DocumentCode :
816410
Title :
A single-chip 802.11a MAC/PHY with a 32-b RISC processor
Author :
Fujisawa, Toshio ; Hasegawa, Jun ; Tsuchie, Koji ; Shiozawa, Tatsuo ; Fujita, Tetsuya ; Saito, Toshitada ; Unekawa, Yasuo
Author_Institution :
SoC R&D Center, Toshiba Corp., Kawasaki, Japan
Volume :
38
Issue :
11
fYear :
2003
Firstpage :
2001
Lastpage :
2009
Abstract :
An 802.11a compliant medium access control (MAC) and physical layer (PHY) processing chip has been successfully fabricated in 0.18-μm CMOS. Thirty million transistors are integrated on a 10.91×10.91 mm2 die housed in a 361-pin PFBGA. The MAC functions are fully implemented by firmware on an embedded 32-b RISC processor, 4-Mb SRAM, and hardware acceleration logic. The PHY supports a complete set of data rates up to 54 Mb/s. Immediate PS-Poll response is realized by the hardware-centric architecture, which can reduce the power consumption of the baseband chip and external RF/IF chips by 29% in power-save mode. The newly developed hybrid automatic gain control circuit can adjust receive signal strength to ±1 dB within 2 μs. Required carrier-to-noise ratio is lower than 4.9 dB at 6-Mb/s data rate and 21.7 dB at 54-Mb/s data rate.
Keywords :
CMOS digital integrated circuits; OFDM modulation; VLSI; adaptive equalisers; automatic gain control; carrier sense multiple access; microprocessor chips; reduced instruction set computing; telecommunication computing; wireless LAN; 0.18 micron; 32 bit; 4.9 to 21.7 dB; 6 to 54 Mbit/s; 802.11a compliant medium access control; CMOS IC; MAC functions; PFBGA; RISC processor chip; SRAM; adaptive equalizers; automatic gain control circuit; baseband chip; carrier sense multiaccess; embedded RISC processor; hardware acceleration logic; hardware-centric architecture; hybrid AGC circuit; orthogonal FDM; physical layer; plastic fine pitch BGA package; power-save mode; single-chip 802.11a MAC/PHY; wireless LAN; Acceleration; Architecture; CMOS logic circuits; CMOS process; Hardware; Media Access Protocol; Microprogramming; Physical layer; Random access memory; Reduced instruction set computing;
fLanguage :
English
Journal_Title :
Solid-State Circuits, IEEE Journal of
Publisher :
ieee
ISSN :
0018-9200
Type :
jour
DOI :
10.1109/JSSC.2003.818135
Filename :
1240982
Link To Document :
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